(a) Field of the Invention
The invention relates to video interface technology, particularly to a sink device applied in the DisplayPort interface.
(b) Description of the Related Art
FIG. 1 shows a schematic diagram illustrating a DisplayPort interface coupling a source device and a sink device, and the data flow between the interfaces.
DisplayPort is a new generation digital high-speed audio-video transmission interface promoted by the Video Electronics Standard Association (VESA). DisplayPort utilizes the PCI-EXPRESS Like Link approach to carry the image and audio data on the high-speed symbol clock signal and the receiving end can recover the original image transmission rate and the original audio transmission rate by transmitting a specific frequency ratio packet.
As shown in FIG. 1A, the DisplayPort interface 130 comprises a main link, an auxiliary channel, and a hot plug detect (HPD) signal wire. The auxiliary channel, with low delay (no more than 500 μs) and capable of bi-directional transmission, provides transmission bandwidth (approximately 1 Mbps) to manage the main link and controls the source device 110 and the sink device 120. The sink device 120 can issue interrupt request to the source device 110 through the BPD signal wire.
The main link is a high bandwidth, low delay, uni-directional isochronous streaming transmission interface comprised by one to four data transmission lanes, to provide digital video and audio simultaneous streaming transmission. Each data transmission lane supports two link rates Flink: 1.62 Gbps or 2.7 Gbps. Therefore, the transmission rate of the DisplayPort can be up to 10.8 Gbps. It should be noted that, based on the technical content disclosed in the invention, the above-mentioned link rate Flink should be differenciated from the other two transmission rates, link symbol rate Fsym and pixel rate Fpix. The link symbol rate Fsym indicates the transmission rate of each symbol on the main link. For each data transmission lane, as one symbol generally transmits eight bits, only a portion of the data of a pixel can be transmitted by one symbol, such as the red (R) data in red/green/blue (RGB). In practice, the link symbol rate Fsym is generated by having the link symbol rate Fsym e 1/10th of the link rate Flink and thus has two transmission rates, 162 Mbps or 270 Mbps. For the pixel rate Fpix, it indicates the transmission speed of each pixel generated by the source device 110, and is not related to the link symbol rate Fsym and the link rate Fpix. Besides, the pixel rate Fpix, the link symbol rate Fsym and the link rate Flink are mutually independent.
There is no independent clock signal lane in the DisplayPort. The sink device 120 utilizes data recovery technology to recover the link symbol rate Fsym from the received data streaming. Besides, when the source device 110 utilizes the DisplayPort to transmit data, the pixel rate Fpix to generate the pixel data is independent of the link rate Flink. The source device 110 transmits data on the interface with the link rate Flink. The source device 110 transmits time stamps Mvid [23:0], Nvid [23:0] to the sink device 120 by way of the specific frequency ratio packet of the DisplayPort or the stream attribute packet (actually, the frequency ratio packet of the DisplayPort also comprises audio time stamps Maud and Naud and since the processing method is similar to that of the time stamp, further details will not be repeated herein), for the sink device 120 to recover the pixel clock signal CLKpix (having the pixel rate Fpix). In other words, the sink device 120 can recover the pixel clock signal CLKpix or the pixel rate Fpix utilized by the transmit device 110, according to the symbol clock signal CLKsym (having the link symbol rate Fsym), the time stamp ratio Mvid/Nvid, and the circuit configuration, as shown in FIG. 1B, comprising two frequency dividers 210, 230 and a phase-locked loop (PLL) 220 which comprises a phase frequency detector PFD, a low pass filter LPF, and a voltage-controlled oscillator VCO. That is, there is no relation between the pixel clock signal CLKpix and the symbol clock signal CLKsym generated by the source device 110. The conversion or mapping between these two transmission rates or clock signals is defined by the time stamps Mvid, Nvid, and the mathematical relationship is expressed by: Tpix×Mvid=Tsym×Nvid, and the pixel rate Fpix can be (Mvid/Nvid)×Fsym.
FIG. 2A shows a schematic diagram illustrating the related image attribute parameters of a display frame. FIG. 2B shows a timing diagram illustrating the relationship between the vertical synchronizing signal VS, the horizontal synchronizing signal HS and the data enable signal DE. The main stream attribute packet transmitted by the source device 110 further comprises the following image attribute parameters (Please refer to FIG. 2A): frame width Htotal, frame height Vtotal, left blank width Hstart, top blanking height Vstart, active area width Hwidth, active area height Vheight, vertical synchronizing width WVS, horizontal synchronizing width WHS, and so forth, for the sink device 120 to recover the original frame format, that is, the size and relative position of the active area A and blank (or non-active) area B of a frame.
According to the DisplayPort specification, the sink device 120 utilizes the above-mentioned recovered pixel rate Fpix as the sampling frequency for transmitting the video data to the back-end circuit, and subsequently constructs or recovers the image control signal according to the above-mentioned image attribute parameters. Referring to FIG. 2B, at first the pixel period Tpix and the vertical synchronizing width WVS (the line period is used as the counting unit) are used to construct a vertical synchronizing signal VS, then the horizontal synchronizing signal HS is constructed according to the pixel period Tpix, the frame width Htotal, and the horizontal synchronizing width WHS (the pixel period is used as the counting unit), and finally the data enable signal DE and the field signal FIELD (not shown in the figure), and so forth are constructed according to the pixel period Tpix, the left blank width Hstart, and the active area width Hwidth, so that the video data can be further processed.
However, some environment factors result in deviations of the pixel clock signal CLKpix recovered by the sink device 120. For example, when the frequency of the recovered pixel clock signal CLKpix is different from the frequency of the original pixel clock signal CLKpix of the original source device 110, frequency drift phenomenon occurs. For example, as the number of bits of the time stamps Mvid, Nvid (or Maud, Naud) are far larger than that of the frequency dividers 210, 230 (approximately more than 28), the two divide-by-M and divide-by-N signals inputted to the phase frequency detector PFD, after frequency dividing, to be generated only once over a long period of time, cause the jitter phenomenon in the output of the phase-locked loop 220 of a common sink device 120, and to thereby result in the above-mentioned frequency drift phenomenon. In order to reduce the electromagnetic interference (EMI), the DisplayPort specification supports frequency spreading designs. However, because of such design, Mvid or Maud received by the sink device 120 may have a large offset value. Then, it is easy for the above-mentioned frequency drift phenomenon to happen in the pixel clock signal CLKpix recovered by the sink device 120 according to such offset value. The final image format recovered by the sink device 120 will be different from the image format transmitted by the source device 110 due to the deviation problem of the pixel clock signal CLKpix, resulting in abnormal operations in the back-end circuit (devices such as image scaler, display device, and so forth).